The D Latch and the D flip-flop

It is possible to create a latch which has no race condition, simply by providing only one input to a RS latch, and generating an inverted signal to present to the other terminal of the latch. In this case, the S and R inputs are always inverted with respect to each other, and no race condition can occur. The circuit for a D latch is shown in Figure 2.7.

Figure 2.7:

The D latch is used to capture, or ``latch'' the logic level which is present on the Data line when the clock input is high. If the data on the line changes state while the clock pulse is high, then the output, , follows the input, . This effect can be seen in the timing diagram, Figure 2.8 (a).

The D flip-flop, while a slightly more complicated circuit, performs a function very similar to the D latch. In the case of the D flip-flop, however, the rising edge of the clock pulse is used to ``capture'' the input to the flip flop. This device is very useful when it is necessary to ``capture'' a logic level on a line which is very rapidly varying. Figure 2.8 (b) shows a timing diagram for a D-type flip-flop. This type of device is said to be ``edge triggered'' -- either rising edge triggered (i.e. a 0-1 transition) or falling edge triggered (i.e., a 1-0 transition) devices are available.

Figure 2.8:

Both the D latch and D flip-flop have the following truth table:

		Clock	D	Q
0	1	x	x	1	0
1	0	x	x	0	1
0	0	x	x	1	1
1	1	or 1	0	0	1
1	1	or 1	1	1	0
1	1	0	X

The symbol means a leading edge, or transition as the clock input to the flip flop. For a D latch, it would be the level 1.

source : http://web.cs.mun.ca/~paul/cs3724/material/web/notes/node13.html