SR Bistable Switch Debounce Circuit

Switch Debounce Circuits

One practical use of this type of Set-Reset circuit is as a latch used to help eliminate mechanical switch "Bounce". As its name implies, switch bounce occurs when the contacts of any mechanically operated Switch, Push-button or Keypad is operated and the internal switch contacts do not fully close cleanly, but bounce together first before closing (or opening) when the switch is pressed. This gives rise to a series of pulses as long as tens of milliseconds that an electronic system or circuit such as a digital counter may see as a series of logic pulses instead of one long single pulse and behave incorrectly, for example, it may register multiple counts instead of a single count. Then Set-Reset SR Flip-flops or Bistable Latch circuits can be used to eliminate this problem and this is shown below.

SR Bistable Switch Debounce Circuit

Depending upon the current state of the output, if the Set or Reset buttons are depressed the output will change over in the manner described above and any additional unwanted inputs (bounces) from the mechanical action of the switch will have no effect on the output. When the other button is pressed, the very first contact will cause the latch to change state, but any additional bounces will also have no effect. The SR flip-flop can then be RESET automatically after a short period of time, for example 0.5 seconds, so as to register any additional and intentional repeat inputs from the same switch contacts, for example multiple inputs from the RETURN key.

Commonly available IC's specifically made to overcome the problem of switch bounce are the MAX6816, single input, MAX6817, dual input and the MAX6818 octal input switch debouncer IC's. These chips contain the necessary flip-flop circuitry to provide clean interfacing of mechanical switches to digital systems.

Set-Reset Latches can also be used as Monostable (one-shot) pulse generators to generate a single output pulse, either High or Low, of some specified width or time period for timing or control purposes. The 74LS279 is a Quad SR Bistable Latch IC, which contains 4 individual NAND type bistable's within a single chip enabling switch debounce or monostable/astable clock circuits to be easily constructed.

Gated or Clocked SR Flip-Flop

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only change state when certain conditions are met regardless of the condition of either the Set or the Reset inputs. By connecting a 2-input NAND gate in series with each input terminal of the SR Flip-flop a Gated SR Flip-flop can be created. This extra conditional input is called an "Enable" input and is given the prefix of "EN" as shown below.

When the Enable input "EN" is at logic level "0", the outputs of the two AND gates are also at logic level "0", (AND Gate principles) regardless of the condition of the two inputs S and R, latching the two outputs Q and Q into their last known state. When the enable input "EN" changes to logic level "1" the circuit responds as a normal SR bistable flip-flop with the two AND gates becoming transparent to the Set and Reset signals. This enable input can also be connected to a clock timing signal adding clock synchronisation to the flip-flop creating what is sometimes called a "Clocked SR Flip-flop".

So a Gated Bistable SR Flip-flop operates as a standard Bistable Latch but the outputs are only activated when a logic "1" is applied to its EN input and deactivated by a logic "0".

source : http://www.electronics-tutorials.ws/sequential/seq_1.html